Kilo-instruction Processors
نویسندگان
چکیده
Due to the difference between processor speed and memory speed, the latter has steadily appeared further away in cycles to the processor. Superscalar out-of-order processors cope with these increasing latencies by having more in-flight instructions from where to extract ILP. With coming latencies of 500 cycles and more, this will eventually derive in what we have called Kilo-Instruction Processors, which will have to handle thousands of in-flight instructions. Managing such a big number of in-flight instructions must imply a microarchitectural change in the way the re-order buffer, the instructions queues and the physical registers are handled, since simply up-sizing these resources is technologically unfeasible. In this paper we present a survey of several techniques which try to solve these problems caused by thousands of in-flight instructions.
منابع مشابه
Different approaches using Kilo-instruction Processors
Kilo-instruction processors are a new overall design paradigm to overcome the memory wall problem in superscalar processors. Its philosophy is based on maintaining thousands of in-flight instructions in a scalable and efficient manner using checkpointing mechanisms. This novel paradigm opens a large number of new topics combining other system-level architecture techniques for ongoing research. ...
متن کاملFast Checkpoint/Recovery to Support Kilo-Instruction Speculation and Hardware Fault Tolerance
The increased relative cost of accessing memory is encouraging processor designers to explore deeper uniprocessor speculation (e.g., with branch and value prediction) and consider multiprocessor speculation (e.g., on coherence message types and values). While some mechanisms have been proposed to support deep speculation using speculative multithreading, current mechanisms for conventional proc...
متن کاملKIMP: Multicheckpointing Multiprocessors
Multiprocessors are coming into wide-spread use in many application areas, yet there are a number of challenges to achieving a good tradeoff between complexity and performance. For example, while implementing memory coherence and consistency is essential for correctness, efficient implementation of critical sections and synchronization points is desirable for performance. The multi-checkpointin...
متن کاملExploiting Execution Locality with a Decoupled Kilo-Instruction Processor
Overcoming increasing memory latency is one of the main problems that microprocessor designers have faced over the years. The two basic techniques introduced to mitigate latencies are caches and out-of-order execution. However, neither of these solutions is adequatefor hiding off-chip memory accesses in the order of 200 cycles or more. Theoretically, increasing the size of the instruction windo...
متن کاملSuperscalar instruction issue
learly, instruction issue and execution are closely related: The more parallel the instruction execution, the higher the requirements for the parallelism of instruction issue. Thus, we see the continuous and harmonized increase of parallelism in instruction issue and execution. This article focuses on superscalar instruction issue, tracing the way parallel instruction execution and issue have i...
متن کامل